400G DR4 QSFP-DD Transceiver

CC-QSFD04DR4-12D

Description

CC-QSFD04DR4-12D-MF000, 400GBASE-DR4, hot pluggable optical transceiver is a high-performance solution for 400GE links for up to 500 m over single mode fiber (SMF) with MPO-12 connector. It combines 8x 26.5625 GBd PAM4 electrical lanes into 4x 53.125 GBd PAM4 optical channels in compliance with IEEE 400GBASE-DR4. Superior performance and reliability is achieved through YSOD’s advanced transmitter and receiver design using cooled 4x EA-DFB-LDs and 4x PIN PDs.

Applications

Data Center 400GE 500 m SMF links

400GE to 4x 100GE breakout over 500 m

Switch/Router interconnections

General Description

This document may contain technologies regulated by law [ECCN: 5E001.c.2.d, 5E991 as of August 2020]. In the case of the export of product(s) and/or technologies described in this document, please take the appropriate procedure in conforming to all regulations related to the export.

Specifications within in this document are subject to change without notice. August 27, 2023

FUNCTIONAL DESCRIPTION

CC-QSFD04DR4-12D is a fully integrated, 425 Gb/s optical transceiver for SMF links up to 500 m. CCQSFD04DR4-12D transmits data in compliance with the optical interface specification IEEE Std 802.3-2022 Section 8 400GBASE-DR4. 400GBASE-DR4 specifies the use of 4-level pulse amplitude modulation (PAM4) at 53.125 Gbaud operating at four parallel channels with wavelength on the range of 1304.5-1317.5 nm from four cooled EA-DFB-LDs. The bit rate per lane is 106.25 Gb/s, which produces an aggregate data rate of 425 Gb/s by means PSM to the transmit ports of the MPO-12 connector. The received optical lanes are paralleled from the receive MPO-12 connector ports to 4 PIN-PDs with transimpedance amplifiers (TIAs) to recover the PAM4 for interfacing with the electrical interface.

The electrical interface is in compliance with 400GAUI-8 specified in IEEE Std 802.3-2022 Section 8. 400GAUI-8 specifies the use of eight differential electrical lanes operating at 26.5625 GBd PAM4 per lane. The bit rate per lane is 53.125 Gb/s, resulting in an aggregate data rate of 425 Gb/s that matches the optical line interface. An internal gear box in DSP converts between the eight lanes of the host interface and the four lanes of the line interface.

In addition, by selecting Breakout Mode, CC-QSFD04DR4-12D is complied with the optical interface specification IEEE Std 802.3-2022 Section 8 100GBASE-DR per lane and the electrical interface specification IEEE Std 802.3-2022 Section 8 100GAUI-2 pre two lanes. 100GBASE-DR specifies the use of PAM4 at 53.125 Gbaud and the bit rate per lane is 106.25 Gb/s. 100GAUI-2 specifies the use of PAM4 at 26.5625 Gbaud and the bit rate per lane is 53.125 Gb/s. By means of a 2:1 mux/demux in DSP, 100GBASE-DR optical interface is connected to 100GAUI-2 electrical interface.

The bit error ratio (BER) of the optical interface is required by 400GBASE-R (Aggregation Mode) and 100GBASE-R (Breakout Mode) to be less than 2.4 x 10-4. The host side shall have Forward Error Correction (FEC) capability based on RS(544,514) requirements defined by IEEE Std 802.3-2022 Section 8 to meet the frame loss ratio requirements of 400GE and 4x 100GE.

The form factor of CC-QSFD04DR4-12D is QSFP56-DD Type 2A and is compliant with the hardware and Common Management Interface Specifications (MIS) of the QSFP-DD multi-source agreement (MSA). QSFP-DD modules can support up to eight electrical lanes on the host interface, which is double the number of lanes supported by QSFP28 or QSFP+ modules. The unique feature of QSFP-DD ports is that they are mechanically and electrically compatible with QSFP28 and QSFP+. Hence, the same port can be used to support multiple generations of modules and data rates if the networking hardware is designed for such operation.